The Quantum Substrate: Categorical Structure and the Hardware Maturity Gap

Quantum compilation is a prospective application of Clef’s general systems foundation. The four-tier model in Quantum Optionality starts with automatic inference from types, then obligations derived from graph coeffects, reusable laws for joint concerns retained by PSG hyperedges, and supported cRHL/pRHL relations. Application developers receive the coverage of admitted rules without adding proof attributes to every operation. Quantum-specific unitarity and boundary laws would extend that foundation through domain-library work.

The Categorical Structure of Quantum Mechanics

Abramsky and Coecke’s categorical semantics of quantum protocols gives a compositional account of quantum processes. Its finite-dimensional Hilbert-space model makes the adjoint and tensor product explicit. It is useful to distinguish that pure linear-map setting from the mixed-state semantics needed for noise, measurement and discard.

In concrete terms:

• Objects are finite-dimensional Hilbert spaces (the state spaces of quantum systems)
• Morphisms in the pure setting are linear maps between those spaces; unitary gates are a restricted class of such maps
• The dagger ($\dagger$) assigns to each morphism its adjoint: if $U$ is a unitary gate, then $U^\dagger$ is its conjugate transpose, satisfying $UU^\dagger = U^\dagger U = I$
• The monoidal structure ($\otimes$) captures tensor products: the state space of a composite quantum system is the tensor product of its components

Mixed-state evolution instead acts on density operators through completely positive maps, with trace conditions distinguishing deterministic channels from individual measurement outcomes. An adjoint of a trace-preserving channel need not itself be trace-preserving, so the channel category is not simply the same dagger-compact category. QWIRE Practice gives a formal circuit-language treatment using density matrices and superoperators. A Clef adapter would need to select and preserve the appropriate semantics for each operation.

This is the same adjoint structure that appears in the CDL paper’s treatment of neural networks and in the HPC adjoint method. The forward/backward duality that unifies backpropagation with sensitivity analysis has a third instance in quantum mechanics: unitary evolution paired with its conjugate.

These domains offer useful compositional structures, but their semantics and preservation laws must be established separately. The presence of an adjoint in each does not establish a shared implementation proof.

The Q# Lineage

Microsoft Research’s Q# language provides concrete evidence of the alignment between ML-family languages and quantum computation. John Azariah documented the design process of building Q# from F#: F#’s computation expressions, algebraic data types, and type inference translated naturally to quantum circuit construction because the categorical structures are compatible.

This is not unique to F#. Any ML-family language with higher-order functions and algebraic data types can express quantum circuits. The relevant property is that the language supports composition of typed morphisms, which is the categorical structure that quantum circuits exhibit.

For our Fidelity Framework, these connections motivate investigating how the PSG could retain quantum composition laws, resource requirements, and transfer boundaries. A quantum backend would need a domain interpretation, representation and device profiles, and checked lowering rules. Existing mechanisms for coeffects and joint constraints provide an architectural starting point.

The Hardware Maturity Gap

The categorical compatibility between our software infrastructure and quantum computation does not mean that quantum compilation is imminent. The gap between mathematical structure and practical hardware is substantial, and honest accounting requires stating it plainly.

Gate errors. A device contract needs the errors, durations and noise assumptions for the operations it actually supplies. A headline gate fidelity does not determine an application’s success probability. Error correction adds its own syndrome circuit, decoder and timing requirements, so comparisons need the complete protocol and workload.

Error correction overhead. A code’s data-qubit count is only part of an architecture’s footprint. Syndrome ancillas, state factories, routing and the required logical error rate also matter. Bravyi and colleagues’ bivariate-bicycle memory protocol illustrates the distinction: its example preserves 12 logical qubits using 288 physical qubits in total, including syndrome ancillas, at a modeled physical error rate of 0.1%. The paper compares that memory task with nearly 3,000 physical qubits for a surface-code realization under its stated assumptions.

The Walking Cat Architecture makes a different, system-level proposal for trapped ions. Its fast variant uses a [[70, 6, 9]] code; its dense variant uses [[102, 22, 9]]. The paper’s dense-architecture example provides 110 logical qubits with 2,514 physical qubits and projects about one million T gates per day. These are resource estimates for the declared architecture, not a measured execution or a ratio derived solely from a memory block’s encoding rate.

The memory protocol and the full computing architecture answer different questions. Their resource counts become comparable only after fixing the task, target failure probability, operation schedule, connectivity and noise model.

Gottesman’s Heisenberg representation provides a foundation for reasoning about the stabilizer operations central to these codes. Its efficient classical simulation result is restricted to the admitted operations; arbitrary circuits and non-Clifford resources require a broader account. This is a useful boundary for a compiler to retain when selecting a simulator or instantiating an error-correction law.

Decoherence and timing. A target profile must state gate, idle, measurement and transport errors alongside their durations. A long fault-tolerant schedule relies on repeated correction and timely classical processing; it does not require an individual physical qubit to remain uncorrected and coherent for the whole run. Device and decoder latency belong in the same execution contract.

Connectivity constraints. Moving ions or atoms can make additional interactions available, with transport and scheduling costs that must be included. A processor cannot be treated as having cost-free all-to-all connectivity merely because its particles move. HRL’s silicon prototype explores a different engineering route: cryogenic CMOS control and a three-rail array of 54 exchange-coupled dots, configurable for up to 18 exchange-only qubits. It demonstrates operations and error-correction components on that device; its results do not establish a complete fault-tolerant architecture or a universal resource ratio.

These constraints are hardware limitations, not software limitations. The quantum computing community is addressing them through improved qubit designs and better error-correction codes. Alternative physical substrates (trapped ions, photonic systems, topological qubits) are a parallel line of attack. Progress is real but incremental.

Our compilation sheaf design offers a research vocabulary for retaining compatible facts through such a pipeline. Applying it to quantum error correction would first require a concrete model of circuit operations, errors, and observations, together with a proved connection between any computed obstruction and the property being reported. A noisy gate alone does not establish a non-trivial cohomology class, and a sheaf description alone does not supply an error-correction procedure.

A quantum error-correction library could contribute parameterized laws about a particular code under stated assumptions. Tier 3 dispatch would instantiate admitted laws from the relevant PSG participants and check their premises. Proving preservation between implementations could require a Tier 4 relation. The code, noise model, decoder, and device interface each need a semantic account; their integration into Fidelity remains prospective.

Code design, decoder validation, and physical error reduction supply different kinds of evidence. Empirical decoder performance remains conditional on the evaluated regime. The intended role of the graph is to retain those conditions at the interfaces where another result depends on them, including the distinction between a measured performance estimate and a proved bound.

Resource estimates and decoder convergence results can motivate this research, but they do not validate a compilation-sheaf model of quantum error correction. Relating that model to the selected code and decoder is additional proof work. Meeting a physical device’s latency and noise constraints remains an engineering obligation.

Quantum Compilation as Spatial Lowering

The IonQ walking-cat paper lays out its compilation stack explicitly: application level, compiler instruction set, logical architecture, micro-architecture, device instruction set, device. Every stage is architecture-specific and lowers the representation toward the physical substrate, and the effective “ISA” is the trap geometry itself. The paper’s scope is the upper portion of that stack: the logical architecture and factory-scheduling layers are specified in detail, while the bottom two layers (device instruction set, device) appear as interface boundaries rather than solved implementation. Analog control, real-time decoder integration under latency constraints, and classical/quantum marshaling remain layers above and below the paper’s scope and are the subject of separate efforts. That shape resembles FPGA compilation more closely than CPU compilation. An FPGA flow runs from HDL through synthesis, technology mapping, placement, and routing to a bitstream, with each stage architecture-specific and with the fabric itself as the ‘ISA’ for lack of a better term. The walking-cat micro-architecture is a placement-and-routing problem under a different substrate: which ions occupy which trap zones, which junctions they traverse, how ring-transport schedules interleave with gate operations.

The resource-factory structure in the IonQ paper’s execution schedule is a dataflow-scheduling problem. Memory blocks, magic factories, cat factories, Bell factories, and qubit factories each produce and consume resources on different timescales, and the architecture coordinates heterogeneous production lines whose outputs feed the main computation at different rates under device-geometry constraints. The decomposition from the logical instruction set through the physical instruction set to the device instruction set is a lowering pass whose specifics depend on the target: logical operations (block preparation, destructive measurement, in-block measurement, inter-block measurement, magic state preparation) resolve into physical operations (Viterbi measurement, error-detected measurement, cat-based measurement, cat state production, cat state stitching, physical rotation, H-state preparation), and the resolution is architecture-specific at every level.

Fidelity’s work on heterogeneous and spatial compilation provides relevant experience for investigating this pipeline. The PSG can retain joint placement and resource constraints, while actor orchestration provides a way to describe classical coordination. Quantum gate semantics, resource factories, timing, and device control still require target-specific models and preservation arguments.

What “Quantum-Ready” Means

Given the hardware maturity gap, what does it mean for a software framework to be “quantum-ready”? The meaning is specific and limited.

Architectural compatibility. Target-specific representation selection, coeffect tracking, and cross-target analysis provide places to express quantum requirements. Whether the current representations are sufficient must be established by implementing and validating a quantum target. Categorical similarity does not establish that this integration needs no architectural changes.

Transfer boundary analysis. Preparation and measurement require explicit relations between classical data, quantum states, and classical observations. Layout and numeric conversion contracts can support the classical portions of a hybrid workflow. They do not by themselves justify state preparation, measurement fidelity, or a device’s noise model.

Verification infrastructure. Given a declared device profile and sound domain analysis, graph coeffects could generate checks for supported qubit, connectivity, storage, and timing constraints before a run is submitted. A resource mismatch could then become a design-time diagnostic. Passing these checks would establish the specified constraints, with the device assumptions retained; it would not prove the physical outcome of the run.

Quantum circuit compilation and its domain-law integrations remain prospective. This section describes how the general verification design could accommodate them, with the implementation and semantic work still to be done.

The Hybrid Computing Model

The more immediate value of categorical compatibility is in hybrid classical/quantum workflows, where a classical optimizer drives a quantum subroutine (the variational quantum eigensolver pattern). In this model:

  graph LR
    C1[Classical Optimizer<br>x86, float64] -->|"Parameters θ"| Q[Quantum Circuit<br>QPU, qubit states]
    Q -->|"Measurements"| C2[Classical Post-Processing<br>x86, float64]
    C2 -->|"Gradient estimate"| C1

The classical components run on conventional targets with conventional numeric representations. The quantum component executes a parameterized circuit and returns measurement outcomes. In the design we envision, our PSG would track the full loop: parameter preparation (classical), circuit execution (quantum), measurement (classical/quantum boundary), and gradient estimation (classical).

In that proposed workflow, dimensional inference would check relationships among typed classical parameters. Graph coeffects would retain applicable resource and representation conditions. A quantum domain library would supply the rules needed to interpret the circuit and its observations. BAREWire could carry the classical layout and transfer contracts, while preparation and measurement would retain their separate quantum semantics and device premises.

Bounding the quantum subroutine’s depth can make an experiment more practical, but useful accuracy and total cost still depend on its circuit, noise, measurement count and classical optimization. Shallow depth alone establishes neither quantum advantage nor an error-correction budget. Our DTS/DMM work can support the classical numerical and transfer obligations while those quantum conditions are evaluated.

Timeline Expectations

For the Fidelity framework specifically:

Present. The general systems work supplies the PSG, dimensional types, memory and representation contracts, and the proof-dispatch design. A classical quantum simulator can be treated as a classical numerical program, but proving its relation to ideal circuit semantics requires additional domain laws and numerical analysis. This document does not establish an implemented quantum backend or a verified quantum device interface.

Near-term research. A bounded hybrid workflow is a candidate integration experiment: specify its circuit semantics, classical transfer contract and device assumptions, then compare simulation with the selected device. Resource estimates can help choose that experiment. They do not supply a delivery date or show that the required hardware and decoder integration have already been demonstrated.

Fault-tolerant integration. The next scope would require enough reliable logical operations for a specified workload, together with validated decoding, control and resource scheduling. Cain and colleagues’ neutral-atom study and the walking-cat architecture offer different resource proposals to assess against that goal. Neither proposal is evidence that Clef already supports its target, and comparisons must retain each study’s assumptions.

Long-term. Our aim is to support quantum and classical targets within a common account of types, graph constraints, and preservation through lowering. Achieving that requires checked semantic adapters and target-specific proofs. The shared categorical vocabulary motivates the work; it does not establish the result in advance.

These are engineering waypoints for the framework, conditional on results outside it. The walking-cat architecture, neutral-atom resource study and silicon prototype contribute different forms of evidence: a proposed computing system, an algorithm-specific resource analysis and a demonstrated device. Our Mosca Moment analysis discusses the broader planning question. Here the compiler’s job is to retain the actual assumptions and verified boundaries of whichever target an application selects.

References

[1] S. Abramsky and B. Coecke, “A categorical semantics of quantum protocols,” in Proc. 19th Annual IEEE Symposium on Logic in Computer Science, pp. 415-425, 2004.

[2] F. Tripier, W. C. Chung, J. Young, S. Alam, B. Bjork, A. Brodutch, F. L. Buessen, N. J. Coble, T. Dellaert, D. Maslov, M. Roetteler, E. Tham, M. Webster, M. Ye, J. Gamble, A. Maksymov, J. P. Marceaux, and N. Delfosse, “Fault-Tolerant Quantum Computing with Trapped Ions: The Walking Cat Architecture,” arXiv:2604.19481 (April 2026).

[3] S. Bravyi, A. W. Cross, J. M. Gambetta, D. Maslov, P. Rall, and T. J. Yoder, “High-threshold and low-overhead fault-tolerant quantum memory,” Nature 627, pp. 778-782 (2024). Introduces the bivariate bicycle code family, including the [[144, 12, 12]] Gross code.

[4] M. Cain, Q. Xu, R. King, L. R. B. Picard, H. Levine, M. Endres, J. Preskill, H.-Y. Huang, and D. Bluvstein, “Shor’s algorithm is possible with as few as 10,000 reconfigurable atomic qubits,” arXiv:2603.28627 (March 2026).

[5] Google Quantum AI, “Safeguarding Cryptocurrency by Disclosing Quantum Vulnerabilities Responsibly,” March 30, 2026. https://research.google/blog/safeguarding-cryptocurrency-by-disclosing-quantum-vulnerabilities-responsibly/

[6] Members of the HRL Quantum Team and Collaborators, “A digitally controlled silicon quantum processing unit,” arXiv:2604.16216 (April 2026). A prototype integrating cryogenic CMOS control, superconducting ribbon-cable interconnect, and a three-rail 54-quantum-dot silicon chip configurable to 18 exchange-only qubits.